Low distortion successive approximation register (SAR) analog-to-digital converters (ADCs) and associated methods

ABSTRACT

An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V ref =M*V DD , where M&lt;1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where V ref =M*V DD , where M&lt;1, wherein the first capacitor having a capacitive value that is equal to (1−M)times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V IN ) signal as the second input to the comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of U.S. patent application Ser. No. 16/139,146, filed Sep. 24, 2018, which claims priority to U.S. Provisional Patent Application No. 62/564,351, filed Sep. 28, 2017 and entitled “Low Distortion ADC Techniques,” both of which are incorporated herein by reference in their entireties.

FIELD

The technology described in this disclosure relates generally to analog-to-digital converters (ADCs) and more particularly to successive approximation register (SAR) ADCs and associated methods.

BACKGROUND

A successive approximation register (SAR) analog-to-digital converter (ADC) converts a sampled analog voltage into a discrete digital representation by using a binary search through possible quantization levels before finally converging upon a digital output. The sampled voltage may be sampled from a continuous analog signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice of the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 depicts an example diagram illustrating voltages associated with inputs to an ADC in accordance with some embodiments.

FIGS. 2A-2B illustrate settling speed of a large capacitor supplied by a relatively small voltage.

FIG. 3 depicts a block diagram of aspects of an SAR ADC.

FIG. 4 depicts an example diagram of components of an SAR ADC in accordance with some embodiments.

FIG. 5 depicts an example diagram of components of an SAR ADC in accordance with some embodiments.

FIG. 6 depicts example diagrams of circuit components of an SAR ADC in accordance with some embodiments.

FIGS. 7A-7B depict example diagrams of circuit components of an SAR ADC in accordance with some embodiments.

FIG. 8 depicts an example diagram of circuit components for use in a differential SAR ADC in accordance with some embodiments.

FIGS. 9A-9C depict example diagrams of plots of signal levels during use of the exemplary SAR ADC of FIG. 8, in accordance with some embodiments.

FIG. 10 depicts an example flow chart for performing analog to digital conversion using an SAR ADC in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The details of the methods and devices of the present disclosure are described in the attached disclosure and drawings. It should be noted that the present technology is not limited to ADCs, but also is applicable to other circuitry into which an SAR, S/H circuit, DACs, or other described circuitry suitably can be integrated.

The present disclosure relates to a low distortion analog-to-digital converter (ADC) that provides consistent performance when an analog input signal (V_(IN)) that is being converted to a digital approximation is smaller than a reference signal voltage level. FIG. 1 illustrates a situation in which a V_(IN) differential input signal 20 to be sampled has a maximum peak-to-peak voltage of 0.67V_(DD). For example, differential input signal 20 may be a sinusoid varying between 0.335V_(DD) and −0.335V_(DD). Input signal 20 is sampled by an ADC 10. ADC 10 is supplied by an input voltage supply of V_(DD) which is greater than the input signal 20 maximum peak to peak voltage. Supply voltage V_(DD) is selected for logic speed concerns. As one will appreciate in high speed semiconductor device applications, logic speed of the SAR ADC is affected by rise times within logic circuits, and rise times are directly affected by supply current. A larger supply voltage applied to a given logic circuit line will experience a larger current leading to faster rise times.

When a sampled signal, e.g. 20, is smaller than a supply voltage, e.g. 12, an external reference voltage is typically used when implementing an, e.g. SAR ADC 10. A reference voltage may selected based on maximum peak-to-peak voltage of an expected V_(IN) 20. Following the example above, for example a reference signal V_(ref) may be 0.375 V_(DD), when a variable voltage V_(IN) to be converted to digital has a maximum expected voltage of less than 0.375 V_(DD) e.g. max. V_(IN)=0.335 V_(DD), where peak-to-peak voltage of V_(IN) is 0.67V_(DD). Because, as it will be appreciated, an SAR ADC performs a binary search of values relative to a reference voltage, if the reference voltage is higher than expected V_(IN) then unnecessary time and resources are expended searching unnecessary values. Thus, having a Vref appropriately selected based on the maximum expected V_(IN) optimizes performance of the SAR ADC.

In known implementations, SAR ADC, e.g. 10, may be supplied directly by V_(ref), but performance may suffer as a result of a smaller supply voltage because rise times increase thereby reducing the speed of a device's logic circuits.

Alternatively, an external or internal Vref generator is relied upon. For example an SAR ADC, e.g. 10, may be supplied by V_(DD), and receive an external or internally Vref from a low drop out (LDO) voltage converter (not illustrated). This solution, however, impacts both area and power considerations as one will appreciate. Another known solution is to amplify input signal V_(IN) to an amplified input signal proportional to V_(DD), but this introduces potential for error arising from linearity concerns. Another known solution is to implement a resistor divider network to obtain Vref, which is easier for design and routing but increases power consumption and speed concerns, because current and required decoupling capacitors for driving an ADC may be relatively larger.

Also, FIGS. 2A and 2B illustrate speed concerns that arise in known methods using a simplified representational circuit 30. FIG. 2A illustrates how slow rise times lead to slow voltage settling, which can lead to incorrect decisions, when as illustrated in FIG. 2B, for example Vref of 0.375V_(DD) drives capacitors of an SAR ADC (illustrated as one capacitor, but may be many capacitors as one will appreciate). As V_(IN) 20 falls, V_(ref) provides charge to V_(cap) 34 via current i_(cap) 36 that is proportional to V_(ref) 32. Thus, the rise time of V_(cap) 34 responsive to V_(IN) 20 is negatively impacted by a low V_(ref) 32. This is because speed concerns arise when a driving voltage or current cannot fully develop during an SAR ADC conversion period (discussed further below).

The present methods and devices can overcome such performance degradation in an SAR ADC with an improvement in an SAR ADC's footprint. An improved SAR ADC is obtained by configuring a most-significant bit (MSB) capacitor of the internal DAC (i.e. the largest capacitor) to take input from V_(DD) or other suitable voltage source(s), rather than from V_(REF). As a result, the high speed semiconductor SAR ADC can operate at high speeds with relatively consistent performance in terms of speed. Furthermore, one or more more-significant bits can also take a supply voltage from V_(DD) further increasing the speed in which voltages develop.

An SAR ADC in accordance with this disclosure, also simplifies V_(ref) design, precluding the need for a LDO based implementation, and the capacitors driven by V_(ref) may be made smaller, thereby increasing voltage settling speed on those capacitors. In an exemplary embodiment of an 8 bit 500 pF unit capacitor ADC design in accordance with this disclosure, for example, realizes a 500% increase in speed while requiring 25% of the area of known solutions and also substantially reduce the size of necessary decoupling capacitors.

For example, FIG. 3 depicts an example diagram of components of a successive approximation register (SAR) analog-to-digital converter (ADC) 30 in accordance with some embodiments. As illustrated in FIG. 3, an SAR ADC can include an SAR sub-circuit 33 configured to supply a parallel n-bit digital word 33′ to an internal digital-to-analog converter (DAC) 34 that includes a capacitor bank 34′ and switching components (not particularly illustrated here). The SAR 33 output 33′ which is provided to DAC 34 can include a digital code or word that converges on an approximation of a sampled voltage sampled from analog input signal V_(IN). The DAC 34 relies on a reference voltage to generate an internal analog voltage based on the output 33′, and provides that internal analog voltage to a comparator in a manner such as described below with reference to FIGS. 4 and 5. A V_(ref) is selected in view of the maximum voltage of an input signal V_(IN).

As provided herein, in order to increase the performance of an SAR ADC 30, when the most significant bit (MSB) and/or one of the more significant bits of the SAR 33 input to the internal DAC 34 of the SAR ADC is set, one or more associated capacitors within capacitor bank 34′ respectively can be driven by the supply voltage V_(DD) or V_(SS), or other suitable voltage(s), rather than by the reference voltage (V_(REF)) alone. By respectively driving these capacitors with V_(DD) or V_(SS) or other suitable voltage, the speed of the more significant bits can be faster, and the design of the V_(REF) supply can be simplified. By “more significant bits” and “less significant bits” it is meant bits that are less significant than the MSB, and optionally can include the least significant bit (LSB). In examples that include both “more significant bits” and “less significant bits,” the “more significant bits” can be more significant than the less significant bits, and the “less significant bits” can be less significant than the more significant bits. It should be appreciated that even in embodiments including a plurality of bits that are less significant than the MSB, such embodiments can be considered to include “more significant bits” but not “less significant bits” or to include “less significant bits” but not “more significant bits.”

Aspects of an exemplary 4-bit DAC 400 that may be used in an SAR ADC (e.g. 500 illustrated in FIG. 5 discussed below) in accordance with this disclosure is illustrated in FIG. 4. DAC 400 for example may correspond to aspects of DAC 500, where each switch S₁-S₄ 402, 404, 406, 408 is controlled by signals D_(N-1), D_(N-2), . . . D₀ (these control signals not particularly illustrated in FIG. 4). Compare 428 may correspond to comparator 520, node 426 may correspond to node 512 and node 420 may correspond to node 542.

As shown DAC 400 includes a comparator 450 with an inverting input coupled to a first node 420 and an inverting input coupled to a second node 426. The first node 420 is coupled to capacitors C₁-C₄ (412, 414, 416, 418) and switch S₅ 410. S5 410 is coupled between node 420 and VSS 422. Comparator 450 also includes a non-inverting input coupled to node 426, which is also coupled to VSS 422. Comparator 450 also includes an output providing an output signal to output node 428, which is coupled to an SAR in a similar manner as output node 528 as shown in FIG. 5 (discussed below). Each of capacitor C₁-C₄ is further coupled to S₁-S₄ (402, 404, 406, 408). It will be appreciated that this is but one implementation of an SAR ADC, and that there are many ways that a DAC may be implemented for the purposes of an SAR ADC in combination with a comparator. Here, in this example, the comparator is configured to compare a voltage on node 420 with VSS 422 on node 426. Other configurations may instead compare a DAC output on node 420 with, e.g. VIN, or other desired voltages. One will appreciate how various components of the DAC can be organized depending on how the comparison is made. The exemplary configuration shown here is referred to as a charge redistribution configuration. In the exemplary embodiment depicted in FIG. 4, comparison is made to VSS 422. In embodiments VSS 422 is ground, in other embodiments VSS 422 is any suitable voltage. For the purpose of this example, VSS 422 is ground. Capacitor C_(RED) 444 is a redistribution capacitor selectably coupling node 420 to V_(DD) 424 or V_(SS) 422 or V_(x) through switch S₇.

As depicted, switches S₁-S₆ are set in what is referred to as track mode, such that V_(IN) is constantly charging and discharging the parallel combination of capacitors. A hold mode is initiated by opening switch S₆, an input switch, thereby leaving the sampled analog voltage sampled from V_(IN) on the capacitor array (412, 414, 416, 418). Switch S₅ is then switched is then opened allowing the voltage at node 420 to move (or be redistributed) as each switch is manipulated. Switches S₁-S₄ are known as bit switches as each is controlled by a single bit of the SAR N-bit digital word output (shown in FIG. 5 as D_(N-1)-D₀). Switch S₁ corresponds to the MSB of the SAR output, S₄ corresponds to the LSB, and S₂-S₃ correspond to more significant bits than S₄ and less significant bits than S₁.

To illustrate the techniques of the present disclosure, it is helpful to consider exemplary DAC 400 in view of known SAR ADC DAC implementations. In known SAR ADC DAC configurations (not illustrated) C_(RED) would be omitted, C₁=C_(U), C₂=C_(U)/2, C₃=C_(U)/4, C₄=C_(U)/4, where C_(U) is a unit capacitance and the total capacitance of the parallel combination of C₁-C₄ is 2C_(U), and node 440 is also coupled to V_(ref) 432 instead of to V_(DD) 424 (i.e. supply) as in accordance with FIG. 4 of various embodiments of the present invention. Thus, in known DACs for an SAR ADC when switches S₁-S₄ are coupled to VSS 422, ground, a voltage equal to −V_(IN) (as V_(IN) is sampled when switch S6 is opened, but for simplicity referred to here as simply V_(IN)) appears on node 420. When S1 coupled to V_(ref), (e.g. by setting bit D_(N-1) in SAR 530), by simple voltage division across C₁ a voltage equal to V_(ref)/2 is added to −V_(IN). The comparator then makes the MSB decision by comparison −V_(in)+V_(ref)/2 to VSS. Based on this comparison, a corresponding SAR, e.g. 530, either leaves S1 connected to Vref, or connects it to ground depending on the comparator output (which, e.g., may be high or low depending on whether the voltage at node 420 is negative or positive). The SAR MSB is set accordingly (for example, the MSB=0 when comparator output is high, and MSB=1 when comparator output is low).

This process is repeated for each switch S2-S4 as the SAR tests and sets or resets each bit (i.e. sets to 0 or 1). Thus, each bit of the SAR output adds a binary weighted voltage: S1 adds either 0 or Vref/2; S2 adds either 0 or Vref/4; S3 adds either 0 or Vref/8; and S4 adds either 0 or Vref/8. When this process completes, the SAR has either set or reset each bit, and the resulting 4-bit word is the digital approximation sampled VIN. This resulting 4-bit word is then output from SAR (not particularly illustrated in FIG. 4, but see N bit output 560 corresponding to DN-1, DN-2, . . . , D0), typically along with an EOC signal to announce to an external circuit that the convergence is complete and a valid digital word is available. This process of resolving each bit of the SAR output by testing each bit through a DAC using a capacitor array is referred to as a binary search that performs a successive approximation algorithm.

Implementing a successive approximation algorithm using a capacitor array in this way normally depends on the precise selection of capacitors, and successively tying each to the same Vref. Because a successive approximation register (SAR) individually compares an input voltage to the midpoint of one of n ranges to determine the value of 1 bit, one will appreciate that capacitor values are selected based on the overall circuit design and desired digital resolution of the SAR ADC (i.e. the number of bits of the digital approximation where more bits results in finer resolution). In the example above, total capacitance was 2CU, with a MSB capacitor equal to CU and binary weighted values corresponding to powers of two with a resolution of V_(ref)/8. One will appreciate that any suitable capacitor scheme may be implemented. In another example, a 12 bit SAR ADC has a LSB switched across a capacitor having capacitance C_(U), and a MSB corresponding to 1024*C_(U) for a total capacitance of 2048C_(U).

In accordance with some embodiments of the present invention, instead of coupling S1 to V_(ref), S1 is coupled instead to VDD. This has the advantage of allowing the large capacitor C1 to be driven by VDD instead of the relatively smaller Vref, increasing the speed at which voltages develop on node 420. In embodiments, other more significant bits may also be coupled to VDD, but as illustrated only C1 is coupled to VDD. By driving the MSB (and in embodiments more significant bits) C1 drives more current. This simplifies the design of a supply for Vref by reducing the amount of current that is required from Vref supply, and this also speeds up the speed at which MSB voltages develop. But the change in supply voltage to C1 from Vref to VDD requires that the capacitor sizes be modified to correct the equation performed by the successive approximation algorithm. That is instead of adding Vref/2 to node 420, MSB capacitor C1 now adds VDD/2. Therefore, MSB caps are reduced accordingly, but to ensure the algorithm's equation remains correct, the MSB capacitance is added back through capacitor C_(RED). Thus, when an MSB is driven by VDD (i.e. when MSB is set) C_(RED) is selectably tied to VDD 424 through switch S₇, and in a sample configuration S7 is coupled to VSS 422. As depicted switch S7 may also tie to VX, which is any suitable voltage as dictated by design considerations, and may in embodiments float.

In the exemplary embodiment depicted, the MSB capacitor size is reduced to account for the altered weights accorded to each bit switch S₁-S₄ (412, 414, 416, 418). For example, in the embodiment shown in FIG. 4, to add back the altered resistance C₁=C_(U)*M, where V_(ref)=M*V_(DD), and the value of C_(RED) is (1−M)C₁. Thus, in accordance with this disclosure, capacitors {C_(RED), C₁, C₂, C₃, C₄} take the values {(1−M)C_(U), M*C_(U), C_(U)/2, C_(U)/4, C_(U)/4}.

In other embodiments, a MSB and one or more more-significant bits are driven by VDD, while the remaining take Vref. Thus, assuming in the example above C1 and C2 are driven by VDD (as opposed to only C1), capacitors {C_(RED), C₁, C₂, C₃, C₄} take the values {(1−M)(C_(U)+C_(U)/2), M*C_(U), M*C_(U)/2, C_(U)/4, C_(U)/4}.

In general, for any switched capacitor SAR DAC having capacitors {C_(N), C_(N-1), . . . , C_(N-Q), C_(N-Q-1), . . . , C₂, C₁, C₀}, where each capacitor having an index greater than N-Q is driven by VDD, and where V_(REF)=M*V_(DD), such a SAR ADC can be implemented in accordance with this disclosure by reducing the capacitors C_(N), C_(N-1), . . . , C_(N-Q) by M such that modified capacitors {C_(XN), C_(XN-1), . . . , C_(XN-O)}={M*C_(N), M*C_(N-1), . . . M*C_(N-Q)}, and the reduced amount of capacitance is added back through C_(RED)=(1−M){C_(N), C_(N-1), . . . , C_(N-Q)}.

Thus, in the exemplary embodiment above for V_(ref)=M*V_(DD) where M<1, (e.g. M=⅜, following the example discussed above in reference to FIG. 1 such that Vref=0.375V for VDD=0.9V, where maximum V_(IN)=0.300V), capacitor 444 C_(RED)=(1−M)*C_(U), and capacitors 412, 414, 416, 418 take the values {M*C_(U), C_(U)/2, C_(U)/4, C_(U)/4}.

To further increase accuracy, a sample and hold (S/H) technique can be employed to hold a value of node 430, whereby once a sampled voltage, e.g., of a high frequency signal, develops on capacitors supporting a V_(IN) line, the V_(IN) line can be disconnected by switch S6 442, such that the voltage for conversion remains applied to the SAR ADC, while the V_(IN) signal continues to vary according to its frequency. This is particularly advantageous when switch S₆ is a MOSFET transistor exhibiting a drain-source capacitance in line with node 430.

FIG. 5 depicts an exemplary configuration of a successive approximation register (SAR) analog-to-digital converter (ADC) in accordance with some embodiments. SAR ADC 500 includes sample-and-hold (S/H) circuit 510, comparator 520, SAR 530, and digital-to-analog converter (DAC) 540. S/H circuit 510 receives as input an analog input voltage (V_(IN)) which is to be digitized, samples and holds that voltage for a specified amount of time, and outputs the sampled and held voltage. Comparator 520 can have an output, a first input, and a second input, and can include, for example, an operational amplifier. Comparator 520 can be coupled to VSS on node 512 as a second input, and also can be coupled to node 542 which receives a DAC 540 generated analog signal. Thus, comparator 520 receives an internal analog voltage at the first input from node 542 that the comparator compares to VSS. SAR 530 (and optionally DAC 540) may be coupled to a source of an internal or external clock signal, e.g. clock 546, as well as to comparator 520 so as to receive the output of the comparator's comparison between VSS and the internal analog voltage, and also is coupled to a source of a clock signal, e.g. clock 546. Nothing in this exemplary configuration is intended to be limiting, and many configurations are possible. For example, an SAR ADC in accordance with the present invention may alternatively be an asynchronous implementation of an SAR ADC that does not require a clock. Also, while illustrated as comparing VSS to the DAC 540 output, as illustrated above with respect to FIG. 4, alternatively a comparison may be made with another suitable voltage. In other embodiments, (e.g. such as the embodiment shown in FIG. 7B) V_(IN) is supplied through the DAC while, e.g., V_(DD) may develops on the non-inverting input node during a track mode configuration. In other embodiments, the SAR ADC may be a fully differential implementation, in which differential voltages are compared, thus converging on each other to obtain an output approximation.

As depicted in FIG. 5, SAR 530 is coupled to comparator 520 and to DAC 540 and configured to receive the output of the comparator as input and to generate based thereon a parallel digital output, which can include an approximate digital word or code (D_(N-1), D_(N-2), . . . D₂, D₁, D₀) of V_(IN), which can have a most significant bit (e.g., D_(N-1)) and a plurality of less significant bits (e.g., D_(N-2), . . . D₂, D₁, D₀) (some of which bits can be referred to as being more significant bits). Based on the parallel digital output, e.g., (D_(N-1), D_(N-2), . . . D₂, D₁, D₀) and based the combination of voltages which it receives, DAC 540 generates the internal analog voltage that is provided to the first input of comparator 520. For example, DAC 540 converts the digital word or code received from SAR 530 into an analog signal for comparison by comparator 520. Control circuitry (not specifically illustrated), such as any suitable combination of hardware, e.g., a shift register block, control logic, and the like such as can be implemented using application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like, and/or software implemented by a data processing unit, can be coupled to each of S/H circuit 510, comparator 520, SAR 530, and/or DAC 540 and configured so as to perform operations such as described herein.

The SAR ADC 500 illustrated in FIG. 5 can be configured so as to apply a binary search algorithm as described above to determine the closest digital word or code to match the input signal V_(IN). For example, SAR 530 can be configured to perform a binary search to test each possible bit for V_(IN), wherein beginning with the most significant bit (MSB) each bit is tested by comparing, by comparator 520, the internal analog signal generated by DAC 540, and based upon comparator 520 sensing that the internal analog signal exceeds the V_(SS), comparator 520 asserts a signal causing SAR 530 to de-assert the tested bit. For example, during use, SAR logic (not specifically illustrated) coupled to SAR 530 can initialize the SAR so that the MSB is equal to 1. If the internal analog voltage generated by DAC 140 exceeds V_(SS), the output of comparator 520 causes SAR 530 to reset the bit, otherwise the bit is left a 1. Then the next bit is set to 1, and the test is performed again. This continues through all the bits, thereby performing a binary search until each bit in the SAR is tested. The final resulting bit sequence is the digital approximation of the sampled input signal, which sequence is then output by the SAR 530 at the end of conversion (EOC) on N bit output 560. As described above with respect to FIG. 4, MSB D_(N-1), and one or more more-significant bits, may be driven by V_(DD), whereas less significant bits are driven by Vref. Thus, node 542 may be selectively coupled through a C_(RED) to VDD and MSBs' and one or more significant bits' associated capacitors have a modified size to account for being driven by VDD as described with respect to FIG. 4 above.

Various configurations of aspects of an SAR ADC in accordance with the present disclosure are described in greater detail below with reference to FIGS. 6, 7A-7B, and 8. In nonlimiting examples such as described below with reference to FIGS. 6, and 7A-7B, an approximation of V_(IN) can be generated

For example, FIG. 6 depicts an example diagram of components of circuit components a general case SAR ADC in accordance with some embodiments. FIG. 6 is not intended to illustrate an entire DAC, rather it is intended to illustrate how various embodiments differ from known SAR ADCs. Whereas in known SAR ADCs each capacitor is selectably driven by a V_(REF) signal, in various embodiments more significant bits, i.e. 642-645 are selectably driven by V_(DD), while less significant bits are selectably driven by V_(REF). Also, while comparator 620 is illustrated with node 621 coupled to the inverting terminal this is not intended to be limiting; as one of skill in the art will appreciate, the comparator inputs may be configured as desired based on overall circuit design or designer preference (e.g. whether an SAR, e.g. 530, expects a high or a low bit when 542 is greater than or less than 512). FIG. 6 may correspond to a similar SAR ADC as shown in FIG. 5, where comparator 620 corresponds to comparator 520, and capacitors 641-649 are aspects of DAC 540. Whereas in the embodiment illustrated in FIG. 5 compares the internal analog signal to VSS, in other embodiments, a comparison is made between the internal analog signal and V_(IN), for example as in the embodiments illustrated in FIG. 7A. Thus, node 621 may correspond to node 512.

Comparator 620 can be configured similarly as described above with reference to FIG. 4. DAC components 640 can correspond to components of DAC 540 described above with reference to FIG. 5, and can include first capacitor 641 associated with the added back capacitances from capacitors C1x-C4x (642, 643, 644, 645) and connected to a supply voltage V_(DD) or V_(SS); second, third, fourth, and fifth capacitors 642, 643, 644, and 645 associated with more significant bits and each coupled to supply voltage V_(DD); and sixth, seventh, eighth, and ninth capacitors 646, 647, 648, and 649 associated with less significant bits and each coupled to reference voltage V_(REF). In the example shown, “C” denotes unit capacitance. In one nonlimiting example, V_(REF)=V_(DD)*M, where M is equal to ⅜ or other suitable fraction less than one where an input voltage is 600 mV peak-to-peak and a supply voltage is 900 mV. V_(REF) is determined by the signal that is being sampled, such that V_(REF) is about the maximum expected voltage of a varying input signal V_(IN).

In the nonlimiting, exemplary embodiment illustrated in FIG. 6, first capacitor 641 can have a capacitance of C_(RED)=C1+C2+C3+C4−C1x−C2x−C3x−C4x, where C1=64C, C2=32C, C3=16C, and C4=8C, and where C is a unit capacitance; second capacitor 642 can have a capacitance of C1x=C1*M; third capacitor 643 can have a capacitance of C2x=C2*M; fourth capacitor 344 can have a capacitance of C3x=C3*M; fifth capacitor 645 can have a capacitance of C4x=C4*M; sixth capacitor 646 can have a capacitance of 4C; seventh capacitor 647 can have a capacitance of 2C; eighth capacitor 648 can have a capacitance of C; and ninth capacitor 649 can have a capacitance of C. Other exemplary voltages and capacitances and numbers of capacitors suitably can be used.

In the exemplary DAC components illustrated in FIG. 6, the capacitors associated with the more significant bits (e.g., second, third, fourth, and fifth capacitors 642, 643, 644, 645) respectively are driven by the supply voltage V_(DD) rather than by V_(REF). Because these capacitors can drive more current than the capacitors associated with the less significant bits (e.g., sixth, seventh, eighth, and ninth capacitors 646, 647, 648, 649), connecting the capacitors associated with the more significant bits can make the V_(REF) supply source design easier and/or can make the speed for the more significant bits faster, because Vref supply need not be designed to provide sufficient current to drive the larger capacitors 642, 643, 644, 645. Additionally, or alternatively, the decoupling capacitor for the V_(REF) supply (not illustrated) can be made smaller, due to the driving current being significantly smaller thereby simplifying the design of an external V_(REF) supply. The same total capacitance as in standard successive approximation techniques can be maintained by adding back the reduced capacitances, e.g., to C_(RED), so as to make the equation correct. Table 1 below compares the speed, area of R, and minimum capacitance of the decoupling capacitor for the V_(REF) supply, based on a nonlimiting, exemplary 8 bit/500 fF unit capacitance ADC design, for some embodiments of the present methods and devices as compared to use of a resistive divider to increase V_(REF).

TABLE 1 Present methods and devices Resistive divider Speed >5X   1X Area of R 1X >4X Decoupling capacitor 1X >25X 

As noted above with reference to FIG. 5, S/H circuit 510 optionally can be used at the input of V_(IN), e.g., so that fluctuations in V_(IN) do not impact the A-C conversion through gate to source of a gate capacitor coupling V_(IN) to the SAR ADC circuit as described above. In one exemplary configuration, S/H circuit 510 can include any previously known S/H circuit. In another exemplary configuration, S/H circuit 510 can include a S/H circuit such as described in U.S. patent application Ser. No. 16/135,053, filed Sep. 19, 2018 and entitled “Low Distortion Sample and Hold (S/H) Circuits and Associated Methods for Use with Analog-to-Digital Converters (ADCs)” or U.S. Provisional Patent Application No. 62/564,353, filed Sep. 28, 2017 and entitled “Low Distortion Sample and Hold,” the entire contents of both of which are incorporated by reference herein.

In FIG. 7A, a DAC configuration that develops voltage V_(DD) or V_(X) on the more significant bit capacitor network and V_(REF) on the less significant bit capacitor network, and compares the voltage at node 721 to V_(IN) comparator 720 can be configured similarly as comparator 520 described above with reference to FIG. 5, and can receive as input via line 721 a processed V_(IN) from circuit 710 which can correspond to circuit 510 described above with reference to FIG. 5. DAC components 740 can correspond to components of DAC 540 described above with reference to FIG. 5, and can include first capacitor 741 associated with the add back capacitance and switchably connected to a line carrying supply voltage V_(DD) or V_(SS) or other voltage V_(X) (which may in embodiments be a float voltage) via a switch 781 (only one such switch labeled in FIG. 7A); second and third capacitors 742, 743 associated with an MSB and more significant bits and each is switchably coupled to a line carrying supply voltage V_(DD) or a line carrying V_(SS) via respective switches 781; and fourth, fifth, and sixth capacitors 744, 745, 746 associated with less significant bits and each switchably coupled to a line carrying reference voltage V_(REF) or to a line carrying supply voltage V_(DD) via respective switches 781. In one nonlimiting example, V_(REF)=V_(DD)*M, where M is a constant ratio of V_(REF) to VDD, such as a suitable fraction less than one and dictated by the voltages of the expected sampled signal.

In the nonlimiting, exemplary embodiment illustrated in FIG. 7A, first capacitor 741 can have a capacitance of C′_(RED)=(1−M)*(C_(N)+ . . . +C_(N-Q)); second capacitor 742 can have a capacitance of C′_(N)=M*C_(N), where in one example C_(N)=32C, where C is a unit capacitance; third capacitor 743 can have a capacitance of C′_(N-Q)=M*C_(N-Q), where in one example C_(N-Q)=8C; fourth capacitor 744 can have a capacitance of C_(N-Q-1), where in one example C_(N-Q-1)=4C; fifth capacitor 745 can have a capacitance of C₁, where in one example C₁=C; and sixth capacitor 746 can have a capacitance of C₀, where in one example C₀=C. Other exemplary voltages and capacitances and numbers of capacitors suitably can be used. Additionally, it should be appreciated that one or more of the capacitors designated as associated with more significant bits instead can be designated as associated with a less significant bit, and that one or more of the capacitors designated as associated with less significant bits instead can be designated as associated with a more significant bit.

In FIG. 7B, a DAC configuration that develops voltage V_(IN) each capacitor network, and compares the voltage at node 721′ to V_(DD) or V_(SS) or V_(x) as desired based on design considerations. Comparator 720′ can be configured similarly as comparator 520 described above with reference to FIG. 5, and can receive as input via line 721′ from circuit 710 which can correspond to circuit 510 described above with reference to FIG. 5. DAC components 740′ can correspond to components of DAC 540 described above with reference to FIG. 5, and can include first capacitor 741′ associated with the add back capacitance and switchably connected either to a line carrying supply voltage V_(DD) or V_(SS) or other voltage V_(X) or to a line carrying V_(IN) via a switch 781′ (only one such switch labeled in FIG. 7B); second and third capacitors 742′, 743′ associated with more significant bits and each switchably coupled to a line carrying supply voltage V_(DD) or to the line carrying V_(IN) via respective switches 781′; and fourth, fifth, and sixth capacitors 744, 745, 746 associated with less significant bits and each switchably coupled to a line carrying reference voltage V_(REF) or to the line carrying V_(IN) via respective switches 681′. In one nonlimiting example, V_(REF)=V_(DD)*M, where M is a constant, such as a suitable fraction less than one dictated by the expected sample signal magnitude.

In the nonlimiting, exemplary embodiment illustrated in FIG. 7B, first, second, third, fourth, fifth, and sixth capacitors 741′, 742′, 743′, 744′, 745′, 746′ respectively can have similar capacitances as described above for first, second, third, fourth, fifth, and sixth capacitors 741, 742, 743, 744, 745, 746 described above with reference to FIG. 7A. Other exemplary voltages and capacitances and numbers of capacitors suitably can be used. Additionally, it should be appreciated that one or more of the capacitors designated as associated with more significant bits instead can be designated as associated with a less significant bit, and that one or more of the capacitors designated as associated with less significant bits instead can be designated as associated with a more significant bit.

As another nonlimiting example, FIG. 8 depicts an example diagram of circuit components of a differential SAR ADC in accordance with some embodiments. In FIG. 8, comparator 820 can be configured similarly as comparator 520 described above with reference to FIG. 5, and can receive as input V_(INN) via line 821 (referred to in FIGS. 8 and 9 as SH_OUT_N) from switch 810 which can be any suitable switch, in some embodiments it may be a sample and hold to circuit like circuit 510 described above with reference to FIG. 5. Comparator 820 illustrated in FIG. 8 also can receive as input V_(INP) via line 722 a complementary signal to V_(INN) (referred to in FIGS. 8 and 9 as SH_OUT_P) from switch 811 which can be any suitable switch, in some embodiments it may be a sample and hold circuit like 510 described above with reference to FIG. 5. It will be appreciated from this disclosure that the SAR ADC implemented with DACs 840 and 840′ use two SAR components controlling the switched capacitor of each DAC 840 and 840′.

DAC components 840 and 840′ can correspond to components of DAC 540 described above with reference to FIG. 5, and can include first capacitor 841 or 841′, respectively, associated with the add back capacitances and switchably connected to lines carrying supply voltage V_(DD) or V_(SS) or other voltage V_(X) via a switches 881 (only one such switch labeled in FIG. 8); second and third capacitors 842, 842′, 843, 843′ associated with more significant bits and each switchably coupled to a line carrying supply voltage V_(DD) or a line carrying V_(SS) via respective switches 881; and fourth, fifth, and sixth capacitors 844, 844′, 845, 845′, 846, 846′ associated with less significant bits and each switchably coupled to a line carrying reference voltage V_(REF) or to a line carrying supply voltage V_(SS) via respective switches 881. In one nonlimiting example, V_(REF)=V_(DD)*M, where M is a constant, such as a suitable fraction less than one as dictated by the maximum magnitude expected of V_(INP) and V_(INN). Again, as one will appreciate, an SAR ADC reference voltage is optimally selected in accordance with the maximum voltage of the sampled input V_(INN) signal.

In the nonlimiting, exemplary embodiment illustrated in FIG. 8, first, second, third, fourth, fifth, and sixth capacitors 841, 841′, 842, 842′, 843, 843′, 844, 844′, 845, 845′, 846, 846′ respectively can have similar capacitances as described above for first, second, third, fourth, fifth, and sixth capacitors 641, 642, 643, 644, 645, 646 described above with reference to FIG. 7A. Other exemplary voltages and capacitances and numbers of capacitors suitably can be used. Additionally, it should be appreciated that one or more of the capacitors designated as associated with more significant bits instead can be designated as associated with a less significant bit, and that one or more of the capacitors designated as associated with less significant bits instead can be designated as associated with a more significant bit.

FIGS. 9A-C depict example diagrams of plots of signal levels during use of the exemplary SAR ADC of FIG. 8, in accordance with some embodiments. Exemplary signal levels for SH_OUT_N 921 corresponding to a voltage on node 821, SH_OUT_P 922 corresponding to node 822, V_(DD) levels (two instances in FIG. 9B plot and FIG. 9C plot) levels V_(REF) (two instances in FIG. 9B plot and FIG. 9C plot), and V_(SS) levels (two instances in FIG. 9B plot and FIG. 9C plot) are shown in accordance with some embodiments. It should be appreciated that such signal levels are purely illustrative, and should not be construed as limiting. In the FIG. 9A plot, SH_OUT_N 921 and SH_OUT_P 922 are illustrated converging on a same voltage as the SAR ADC conducts a binary search of values to determine a digital differential voltage value approximating the differential analog voltage between V_(INN) and V_(INP). In the FIG. 9B plot, values corresponding to individual bit switch capacitors are shown as the SAR performs its binary search. As shown for example voltage 942′ corresponding to MSB 842′ and a more significant bit voltage 943′ are switched between VSS and VDD, where as a less significant bit voltage value 946 is switched between VSS and VREF, e.g. as in FIG. 8, less significant bit 846 is driven by VREF. In the example shown every approximately 1/10^(th) of a nanosecond a bit is tested as bit switches are switched thereby adding or removing charge from, e.g. nodes 821 or 822 causing SH_OUT_N 921 and SH_OUT_P 922 to converge on a same voltage corresponding to the differential voltage value between the sampled signals on V_(INN) and V_(INP).

FIG. 10 depicts an example flow chart for performing analog-to-digital conversion using an SAR ADC in accordance with some embodiments. Method 1000 illustrated in FIG. 10 includes an operation of supplying an input voltage (V_(IN)) as a second input to a comparator having an output, a first input, and the second input (1010). For example, comparator 520 illustrated in FIG. 5 can receive V_(IN) at its second input. Method 1000 illustrated in FIG. 10 also can include an operation of supplying the output of the comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having an MSB and a plurality of less significant bits (1020). For example, the output of comparator 520 illustrated in FIG. 5 can be coupled to SAR 530, which generates based thereon a parallel digital output having an MSB and a plurality of less significant bits. Method 1000 illustrated in FIG. 10 also can include supplying the parallel digital output to a DAC to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator (1030). As described above with reference to FIGS. 4, 5, 6, 7A-7B, and 8, a DAC (e.g., DAC 540 illustrated in FIG. 5) includes a capacitor network having a first capacitor associated with the add back capacitance and a plurality of second capacitors. The first capacitor can be coupled between a first line carrying a first voltage and a second line carrying a second voltage. The plurality of second capacitors can be associated with more significant bits, and are associated with capacitors having reduced capacitance, and are coupled between the first voltage and the second voltage. The less significant bits are associated with capacitors having standard capacitance for an SAR ADC, and respectively coupled between the first line and a third line carrying a third voltage.

Accordingly, the present methods and devices provide ADCs, DACs, and associated circuitry that can use suitable voltages to drive respective capacitors within capacitor networks, which provides for improved speed, simplified reference voltage supply design, smaller decoupling capacitors for the reference voltage supply, while maintaining a similar total capacitance.

In one embodiment, an analog-to-digital converter (ADC) device comprises a comparator having an output, a first input, and a second input. And the ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V_(ref)=M*V_(DD), where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where V_(ref)=M*V_(DD), where M<1, wherein the first capacitor having a capacitive value that is equal to (1−M) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V_(IN)) signal as the second input to the comparator.

In another embodiment, a method for performing an analog-to-digital conversion includes supplying an input voltage (V_(IN)) as a second input to a comparator having an output, a first input, and the second input. And supplying the output of the comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having a plurality of more significant bits, including a most significant bit (MSB), and a plurality of less significant bits. And supplying the parallel digital output to a digital-to-analog converter (DAC) to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator, wherein the internal analog signal is generated by voltage division across a plurality of capacitors. The DAC includes a first capacitor network having a first capacitor and a second capacitor network having plurality of second capacitors, and a third capacitor network having a plurality of third capacitors, the first capacitor having a value based the total parallel capacitance of each of the second capacitors and coupled between a first line carrying a first voltage and a second line carrying a second voltage, the plurality of second capacitors associated with the plurality of more significant bits, including the MSB, further wherein the plurality of second capacitors each also coupled between the first line and the second line and having respectively a value based on a ratio of the first voltage to a third voltage that is less than the first voltage, further wherein the plurality of third capacitors are associated with the less significant bits and respectively coupled between the first line and a third line carrying the third voltage.

In yet another embodiment, a DAC includes a capacitor network having a first capacitor and a plurality of second capacitors, the first capacitor being coupled to a first line carrying a first voltage and a second line carrying a second voltage, and the plurality of second capacitors being coupled to the second line and to a third line carrying a third voltage. The first voltage is greater than the third voltage.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

This written description and the following claims may include terms, such as “on,” that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of an SAR, SAR ADC, DAC, S/H circuit, and/or related circuitry described herein can be manufactured, used, or shipped in a number of configurations. 

What is claimed is:
 1. An analog-to-digital converter (ADC) device comprising: a successive approximation register (SAR) configured to generate a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage; a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, wherein the DAC includes: a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio M is equal to the reference voltage divided by the first voltage; one or more first capacitors; and a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor's capacitance is equal to (1−M) times a total capacitance of a parallel combination of the one or more first capacitors, wherein the plurality of second capacitors are associated with the plurality of less significant bits.
 2. The ADC of claim 1, wherein: the SAR is configured to perform a binary search to test each possible bit of the parallel digital output, wherein beginning with the MSB each bit is tested by comparing, by a comparator, the internal analog signal to an input voltage V_(IN), and based upon the comparator sensing that the internal analog signal exceeds the input voltage V_(IN), the comparator asserts a signal causing the SAR to either de-assert the tested bit or to set the tested bit.
 3. The ADC of claim 2, wherein the input voltage V_(IN) is sampled from a varying analog signal by a sample and hold circuit.
 4. The ADC of claim 1, wherein based upon the MSB remaining high during testing, one or more of the first capacitors associated with one or more more-significant bits is tied to a supply voltage V_(DD).
 5. The ADC of claim 1, wherein the SAR implements a successive approximation algorithm.
 6. The ADC of claim 1, wherein the one or more first capacitors is associated with one or more less significant bits in addition to the MSB.
 7. The ADC of claim 1, wherein at the SAR performs a binary search of values of the parallel digital output.
 8. The ADC of claim 1, further comprising a plurality of switches respectively configured to decouple the plurality of second capacitors from the reference voltage.
 9. A method for performing an analog-to-digital conversion, the method comprising: supplying an output of a comparator to an input of a successive approximation register (SAR) to generate based thereon a parallel digital output having a most significant bit (MSB), and a plurality of less significant bits; supplying the parallel digital output to a digital-to-analog converter (DAC) to generate based thereon an internal analog signal, wherein the DAC includes a first capacitor, a plurality of second capacitors, and a plurality of third capacitors, wherein the first capacitor is coupled between a first line carrying a first voltage and a second line carrying a second voltage, wherein the plurality of second capacitors is each switchable coupled between the first line and the second line and having respectively a value less than the first voltage, wherein the plurality of third capacitors is associated with the less significant bits and respectively switchably coupled between the first line and a third line carrying the third voltage.
 10. The method of claim 9, wherein: the SAR performs a binary search to test each possible bit of the parallel digital output, wherein beginning with the MSB each bit is tested by comparing, by the comparator, the internal analog signal to an input voltage (V_(IN)) to the comparator; and based upon the comparator sensing that the internal analog signal exceeds V_(IN), the comparator asserts a signal causing the SAR to either de-assert the tested bit or set the tested bit.
 11. The method of claim 9, wherein the internal analog signal is generated by voltage division across a plurality of capacitors.
 12. The method of claim 9, wherein the first voltage is V_(DD).
 13. The method of claim 12, wherein the first voltage is V_(SS).
 14. The method of claim 13, wherein the third voltage is a reference voltage V_(REF).
 15. The method of claim 9, wherein based upon the MSB being set high and the less significant bits being set low, the internal analog signal is equal to V_(REF)/2.
 16. The method of claim 9, further comprising providing a plurality of switches respectively configured to switchably couple the first capacitor to the first line and to switchably couple the plurality of third capacitors from the third voltage line.
 17. A digital-to-analog converter (DAC), comprising: a first capacitor and a plurality of second capacitors, the first capacitor being coupled to a first line and a second line, and the plurality of second capacitors being coupled to the second line and to a first node switchably coupled by a first switch to a third line carrying a reference voltage, and wherein the first capacitor is not connected or switchably adapted to connect to the third line, wherein the first line carries a first voltage greater than the reference voltage, and wherein a successive approximation register (SAR) controls the first switch.
 18. The DAC of claim 17, wherein the first voltage is a supply voltage V_(OO).
 19. The DAC of claim 17, further comprising a plurality of switches respectively configured to switchably couple the first capacitor to the first voltage when one or more capacitors associated with more significant bits are also switchably coupled to the first voltage, wherein the plurality of switches are controlled by signals from the SAR.
 20. The DAC of claim 17, wherein the SAR performs a successive approximation algorithm. 